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FEATURES Complete Dual 12-Bit DAC No External Components +5 V Single-Supply Operation 10% 4.095 V Full Scale (1 mV/LSB) Buffered Voltage Outputs Low Power: 5 mW/DAC Space Saving 1.5 mm Height SO-14 Package APPLICATIONS Digitally Controlled Calibration Servo Controls Process Control Equipment Computer Peripherals Portable Instrumentation Cellular Base Stations Voltage Adjustment
CS CLK CLK LATCH
+5 Volt, Serial Input, Dual 12-Bit DAC AD8522
FUNCTIONAL BLOCK DIAGRAM
VDD DAC A REGISTER D SDI (DATA) SHIFT REGISTER 12 BANDGAP REFERENCE REF BUF VREF REF BUF DAC A 12 OP AMP A VOUTA
D SDO
DAC B REGISTER 12 DAC B OP AMP B VOUTB
LDA LDB
CONTROL LOGIC
AD8522
MSB RS AGND
DGND
GENERAL DESCRIPTION
The AD8522 is a complete dual 12-bit, single-supply, voltage output DAC in a 14-pin DIP, or SO-14 surface mount package. Fabricated in a CBCMOS process, features include a serial digital interface, onboard reference, and buffered voltage output. Ideal for +5 V-only systems, this monolithic device offers low cost and ease of use, and requires no external components to realize the full performance of the device. The serial digital interface allows interfacing directly to numerous microcontroller ports, with a simple high speed, three-wire data, clock, and load strobe format. The 16-bit serial word contains the 12-bit data word and DAC select address, which is decoded internally or can be decoded externally using LDA, LDB
0.6 0.4
LINEARITY ERROR - LSB
inputs. A serial data output allows the user to easily daisy-chain multiple devices in conjunction with a chip select input. A reset RS input sets the outputs to zero scale or midscale, as determined by the input MSB. The output 4.095 V full scale is laser trimmed to maintain accuracy over the operating temperature range of the device, and gives the user an easy-to-use one-millivolt-per-bit resolution. A 2.5 V reference output is also available externally for other data acquisition circuitry, and for ratiometric applications. The output buffers are capable of driving 5 mA. The AD8522 is available in the 14-pin plastic DIP and low profile 1.5 mm SOIC-14 packages.
PACKAGE TYPES AVAILABLE
VDD = +4.5V TA = -55C, +25C, +85C, +125C +25C -55C
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 +85C
PDIP-14 SO-14
+125C
1024 2048 3072 DIGITAL INPUT CODE - Decimal
4096
Figure 1. Linearity Error vs. Digital Code & Temperature
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD8522-SPECIFICATIONS V (@
ELECTRICAL CHARACTERISTICS
Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage2 Full-Scale Tempco2, 3 MATCHING PERFORMANCE Linearity Matching Error ANALOG OUTPUT Output Current Load Regulation at Half-Scale Capacitive Load3 REFERENCE OUTPUT Output Voltage Output Source Current4 Line Rejection Load Regulation LOGIC INPUTS & OUTPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 Logic Output Voltage Low Logic Output Voltage High TIMING SPECIFICATIONS3, 5 Clock Width High Clock Width Low Load Pulse Width Data Setup Data Hold Clear Pulse Width Load Setup Load Hold Select Deselect Clock to SDO Propagation Delay AC CHARACTERISTICS Voltage Output Settling Time6 Crosstalk DAC Glitch Digital Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current Power Dissipation7 Power Supply Sensitivity
3, 5
DD = +5.0 V otherwise noted)
10%, RL = No Load, -40 C TA +85 C, both DACs tested, unless
Symbol N INL DNL VZSE VFS TCVFS VFSA/B IOUT LDREG CL VREF IREF LNREJ LDREG VIL VIH IIL CIL VOL VOH tCH tCL tLDW tDS tDH tCLRW tLD1 tLD2 tCSS tCSH tPD tS CT Q DFT
Condition
Min 12 -1.5 -1 4.079
Typ
Max
Units Bits LSB LSB mV Volts ppm/C LSB
Monotonic Data = 000H Data = FFFH
0.5 0.5 +0.5 4.095 15 1
+1.5 +1 +3 4.111
Data = 800H, VOUT 3 LSB RL = 402 to , Data = 800H No Oscillation 2.484
1 500 2.500 0.025 0.025
5 3
mA LSB pF V mA %/V %/mA V V A pF V V ns ns ns ns ns ns ns ns ns ns ns s dB nV s nV s
VREF < 18 mV IREF = 0 to 5 mA, Data = 800H
2.516 5 0.08 0.1 0.8
2.4 IOL = 1.6 mA IOH = 400 A 10 10 0.4 3.5 35 35 25 10 20 20 10 10 30 30 20 To 1 LSB of Final Value Signal Measured at DAC Output, While Changing Opposite LDA/B Half-Scale Transition Signal Measured at DAC Output, While Changing Data Without LDA/B VDD = 5.5 V, VIH = 2.4 V or VIL = 0.8 V VDD = 5 V, VIL = 0 V VDD = 5 V, VIH = 2.4 V or VIL = 0.8 V VDD = 5 V, VIL = 0 V VDD = 5%
45 16 38 13 2 3 1 15 5 0.002
80
IDD PDISS PSS
5 2 25 10 0.004
mA mA mW mW %/%
NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V REF pin. Use external buffer if setting up a virtual ground. 5 All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. 7 Power Dissipation is calculated I DD x 5 V. Specifications subject to change without notice.
-2-
REV. A
AD8522
SDI Sf/Hd B A NC DB11 DB10 DB4 DB3 DB2 DB1 DB0 CLK
t CSS
CS
t CSH tLD2 tLDW tPD
tLD1
LD
SDO SDI
tCH
CLK
tDS tCL
tDH
tLD2 tLDW tCLRW
LD RS FS VOUT ZS
tS tS
1 LSB ERROR BAND
Figure 2. Timing Diagram
SERIAL INPUT REGISTER DATA FORMAT
Last D0 DB0 D1 DB1 D2 DB2 D3 DB3 D4 DB4 D5 DB5 D6 DB6 D7 DB7 D8 DB8 D9 DB9 D10 D11 D12 D13 A D14 B
First D15 Sf/Hd
DB10 DB11 NC
Table I. Truth Table
Data Word Sf/Hd
B
A X X X X L L L H H H H
Ext Pins LDA H H X H H H
LDB H H X H H H
DAC Register Loads DACA + DACB with Data from SR Loads DACA with Data from SR Loads DACB with Data from SR No Load No Load Loads DACB with Data from SR, See Note 1 Below No Load Loads DACA with Data from SR, See Note 1 Below No Load Loads DACA + DACB with Data from SR, See 1 Note Below No Load
Hardware Load: L X L X L X L X Software Decode Load: H L H H H H H L H L H H H H
NOTES 1 In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high. 2 External Pins LDA and LDB should always be high when shifting Data into the shift register. 3 symbol denotes negative transition.
1.6mA
SDO
1.6 VOLT
200A
Figure 3. AC Timing SDO Pin Load Circuit
REV. A
-3-
AD8522
PIN DESCRIPTION
Pin SDI CLK CS LDA/B
Function Serial Data Input, input data loads directly into the shift register. Clock input, positive edge clocks data into shift register. Chip Select, active low input. Prevents shift register loading when high. Does not affect LDA and LDB operation. Load DAC register strobes, active low. Transfers shift register data to DAC register. See truth table for operation. Software decode feature only requires one LD strobe. Tie LDA and LDB together or use one of them with the other pin tied high. Serial Data Output. Output of shift register, always active. Resets DAC registers to condition determined by MSB pin. Active low input. Digital input: High presets DAC registers to half scale (800H); Low clears all registers to zero (000H), when RS is strobed to active low. Positive +5 V power supply input. Tolerance 10%. Analog Ground Input. Digital Ground Input. Reference Voltage Output, 2.5 V nominal. DAC A/B voltage outputs, 4.095 V full scale, 5 mA output.
SDO RS MSB VDD AGND DGND VREF VOUT A/B
PIN CONFIGURATION 14-Pin Plastic DIP 14-Lead SO-14
ABSOLUTE MAXIMUM RATINGS*
VOUTA AGND DGND CS CLK SDI SDO
1 2 3
14 VOUTB 13 VREF
AD8522
12 VDD 1
4 (Not To Scale) 11 MSB 5 6 7 10 RS 9 8 LDA LDB
Table II. Truth Tables
VDD to DGND & AGND . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V Logic Inputs and Output to DGND . . . . . -0.3 V, VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD IOUT Short Circuit to GND or VDD . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . . (TJ max-TA)/JA Thermal Resistance, JA 14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . . 83C/W 14-Lead SOIC Package (SO-14) . . . . . . . . . . . . . . 120C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150C Operating Temperature Range . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RS MSB 0 0 1 0 1 X
DAC Register Preset Register Activity Asynchronously Resets DAC Registers to Zero Scale Asynchronously Presets DAC Registers to Half Scale (800H) None Shift Register Shift Register No Effect Shifts Register One Bit, SDO Outputs Data from 16 Clocks Earlier
ORDERING GUIDE
Model AD8522AN AD8522AR
Temperature Range -40C to +85C -40C to +85C
Package Description
Package Option
CS CLK 1 0 X
14-Pin P-DIP N-14 14-Lead SOIC SO-14
The AD8522 contains 1482 transistors.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8522 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD8522
OPERATION
The AD8522 is a complete ready-to-use dual 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for operation. It contains two voltage-switched, 12-bit, lasertrimmed digital-to-analog converters, a curvature-corrected bandgap reference, rail-to-rail output op amps, input registers, and DAC registers. The serial data interface consists of a serial data input (SDI), clock (CLK), and two load strobe pins (LDA, LDB) with an active low CS strobe. In addition, an asynchronous RS pin will set all DAC register bits to zero causing the VOUT to become zero volts, or to midscale for trimming applications when the MSB pin is programmed to Logic 1. This function is useful for power on reset or system failure recovery to a known state.
D/A CONVERTER SECTION
VDD
P-CH
VOUT N-CH
AGND
Figure 5. Equivalent Analog Output Circuit
The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 V internal bandgap voltage. It uses a laser-trimmed R-2R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
Figures 6 and 7 in the typical performance characteristics section provide information on output swing performance near ground and full scale as a function of load. In addition to resistive load driving capability the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability.
REFERENCE SECTION
The internal DAC's output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.638 (= 4.095 V/2.5 V) in order to set the 4.095 V full-scale output (1 mV/LSB). See Figure 4 for an equivalent circuit schematic of the analog section.
BANDGAP REFERENCE VREF 2.5V BUFFER 2R R2 R 2R R1 A V = 4.096/2.5 = 1.638V/V 2R VOLTAGE SWITCHED 12-BIT R-2R D/A CONVERTER 2R R RAIL-TO-RAIL OUTPUT AMPLIFIER VOUT
The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the VREF pin. Since VREF is not intended to drive heavy external loads, it must be buffered. The equivalent emitter follower output circuit of the VREF pin is shown in Figure 4. Bypassing the VREF pin will improve noise performance; however, bypassing is not required for proper operation. Figure 10 shows broad band noise performance.
POWER SUPPLY
The very low power consumption of the AD8522 is a direct result of a circuit design optimizing use of a CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors good analog accuracy is achieved. For power consumption sensitive applications it is important to note that the internal power consumption of the AD8522 is strongly dependent on the actual input voltage levels present on
the SDI, CLK, CS, MSB, LDA, LDB and RS pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. Consequently for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the logic input pins provides the lowest standby dissipation of 1 mA with a +5 V power supply.
SPDT N CH FET SWITCHES
2R
Figure 4. Equivalent AD8522 Schematic of Analog Portion
The op amp has a 16 s typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the "Typical Performance Characteristics" section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 5 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the -10% supply tolerance value of 4.5 V. REV. A
As with any analog system, it is recommended that the AD8522 power supply be bypassed on the same PC card that contains the chip. Figure 12 shows the power supply rejection versus frequency performance. This should be taken into account when using higher frequency switched-mode power supplies with ripple frequencies of 100 kHz and higher. One advantage of the rail-to-rail output amplifiers used in the AD8522 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +4.5 V to +5.5 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8522
-5-
AD8522
is possible down to +4.3 V. The minimum operating supply voltage versus load current plot, in Figure 7, provides information for operation below VDD = +4.5 V.
TIMING AND CONTROL
input register and transferring the 12 bits of data into the decoded address determined by the address bits A and B in the serial input register.
Unipolar Output Operation
The AD8522 has a 16-bit serial input register that accepts clocked in data when the CS pin is active low. The DAC registers are updated by the Load Enable (LDA and LDB) pins. The AD8522 offers two modes of data loading. The first mode, hardware-load, directs the data currently clocked into the serial shift register into either the DAC A or the DAC B register or both depending on the external active low strobing of the LDA or LDB pin. Serial data register bit Sf/Hd must be low for this mode to be in effect. The second mode of operation is software-load which is designed to minimize the number of control lines connected to the AD8522. In this mode of operation the LDA and LDB pins act as one control input taking the present contents of the serial
This is the basic mode of operation for the AD8522. The AD8522 has been designed to drive loads as low as 820 in parallel with 500 pF. The code table for this operation is shown in Table III.
Table III. Unipolar Code Table
Hexadecimal Number in DAC Register FFF 801 800 7FF 000
Decimal Number in DAC Register 4095 2049 2048 2047 0
Analog Output Voltage (V) +4.095 +2.049 +2.048 +2.047 0
Typical Performance Characteristics
5 VDD = +5V TA = +25C 4 5.0 RL TIED TO AGND DATA = FFFH 3 VINH = +5V VINL = 0V 5.2
OUTPUT PULL-DOWN VOLTAGE - mV
100
VFS 1 LSB DATA = FFFH TA = +25C
OUTPUT VOLTAGE - Volts
10
V DD MIN - Volts
4.8 PROPER OPERATION WHEN VDD SUPPLY VOLTAGE IS ABOVE CURVE
VDD = +5V DATA = 000H VIH = 5.0V VIL = 0.0V
4.6
1
+85C
2
4.4
-55C 0.1 +25C
1 RL TIED TO +5V DATA = 000H 0 10 100 1k 10k LOAD RESISTANCE - 100k 4.2
4.0 0.01
0.1 1.0 10 OUTPUT LOAD CURRENT - mA
100
0.01 1 10 100 OUTPUT SINK CURRENT - A 1000
Figure 6. Output Swing vs. Load
Figure 7. Minimum Supply Voltage vs. Load Current
Figure 8. Pull-Down Voltage vs. Output Sink Current Capability
9
80 60
OUTPUT CURRENT - mA
SUPPLY CURRENT IDD - mA
40 20
POSITIVE CURRENT LIMIT
100 90
8
NBW = 1MHz
TA = +25C
TA = +25C 7 6 5 VDD = +5V 4 3 2 1 VDD = +4.5V
DATA = 800H 0 -20 -40 -60 -80 1 2 3 OUTPUT VOLTAGE - Volts NEGATIVE CURRENT LIMIT
200V/DIV
10 0%
100s/DIV
0 0 1 2 3 4 LOGIC INPUT VOLTAGE VINH - Volts 5
Figure 9. IOUT vs. VOUT
Figure 10. Broadband Noise
Figure 11. Supply Current vs. Logic Input Voltage
-6-
REV. A
AD8522
140
POWER SUPPLY REJECTION - dB INPUT
120 100 80
VDD = +5V 200mVAC TA = +25C DATA = FFFH
5V
LD
100 90
204810 TO 204710
RS
5V
100
0V 90
VOUT
4V
OUTPUT
60 40 20 0 10 #299, DAC A VINH = +5V VINL = 0V
VOUT 100mV/ DIV
10 0%
TA = +25C VDD = +5V
TA = +25C VDD = +5V
10 0%
0V
100mV
TIME - 500ns/DIV
500ns
-SR +SR
TIME - 20s/DIV
100
1k 10k 100k FREQUENCY - Hz
1M
Figure 12. Power Supply Rejection vs. Frequency
Figure 13. Midscale Transition Performance
Figure 14. Large Signal Settling Time
40 35 30 TUE = (INL+ZS+FS) SSZ = 300 UNITS VDD = +4.5V TA = +25C
4.11 4.105 VDD = +4.5V NO LOAD SSZ = 300 UNITS
1.6 1.4
ZERO-SCALE VOLTAGE - mV
FULL SCALE VOLTAGE - Volts
4.1 AVG +1 4.095 4.09 4.085 4.08 4.075 -55 -35 -15 AVG AVG -1
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 -35 -15
VDD = +4.5V NO LOAD SSZ = 300 UNITS
FREQUENCY
25 20 15 10 5 0
AVG +1
AVG
AVG -1 5 25 45 65 85 TEMPERATURE - C 105 125
-5 -4 -3 -2 -1 0 1 2 3 4 TOTAL UNADJUSTED ERROR - mV
5
5 25 45 65 85 TEMPERATURE - C
105 125
Figure 15. Total Unadjusted Error Histogram
Figure 16. Full-Scale Voltage vs. Temperature
Figure 17. Zero-Scale Voltage vs. Temperature
100
FULL-SCALE OUTPUT VOLTAGE - Volts
OUTPUT NOISE DENSITY - V/Hz
4.096 4.095 4.094 4.093 4.092 4.091 4.090 4.089 4.088 4.087 4.086 4.085 4.084 0 100 200 300 400 500 HOURS OF OPERATION AT +150C 600 AVG -1 AVG AVG +1 VDD = +4.5V SSZ = 135 UNITS DATA = FFFH SUPPLY CURRENT - mA
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -55 -35 -15 VIN = +2.4V NO LOAD VDD = +5.5V VDD = +5V VDD = +4.5V
V DD = +5V DATA = FFF H TA = +25C 10
1.0
0.1 10
100
1k 10k FREQUENCY - Hz
100k
5 25 45 65 85 TEMPERATURE - C
105 125
Figure 18. Output Voltage Noise Density vs. Frequency
Figure 19. Long Term Drift Accelerated by Burn-In
Figure 20. Supply Current vs. Temperature
REV. A
-7-
AD8522
2.504
2V
VDD
0V
100 90
5V
2.502
AVG +1 AVG
CLK
VREF - Volts
V DD = +4.5V SSZ = 300 UNITS
TA = +25C NO LOAD VDD = +5V
0V
2.500 AVG -1
VREF
0V
VOUT 20mV/ DIV
10 0%
2.496
1V
TIME - 1s/DIV
1s
TIME - 5s/DIV
2.494
2.492 -55 -35 -15
5 25 45 65 85 TEMPERATURE - C
105 125
Figure 21. Reference Startup vs. Time
0
Figure 22. Digital Feedthrough vs. Time
0.05
Figure 23. Reference Voltage vs. Temperature
VREF LOAD REGULATION - %/mA
-0.01
VREF LINE REGULATION - %/Volts
V DD = +4.5V SSZ = 300 UNITS IL = 5mA
V DD = +4.5V TO +5.5V SSZ = 300 UNITS 0.04
-0.02 AVG +3 -0.03 AVG -3 AVG
0.03 AVG 0.02 AVG -3 0.01
AVG +3
-0.04
-0.05
-0.06 -55 -35 -15
5 25 45 65 85 TEMPERATURE - C
105 125
0 -55 -35 -15
5 25 45 65 85 TEMPERATURE - C
105 125
Figure 24. Reference Load Regulation vs. Temperature
Figure 25. Reference Line Regulation vs. Temperature
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Narrow Body SOIC (SO-14)
14-Lead Epoxy DIP (N-14)
14
8 0.1574 (4.00) 0.1497 (3.80)
14 PIN 1 1 0.795 (20.19) 0.725 (18.42)
8
PIN 1 1 7
0.2440 (6.20) 0.2284 (5.80)
7 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.195 (4.95) 0.115 (2.93)
0.3444 (8.75) 0.3367 (8.55) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8 0
0.0196 (0.50) x 45 0.0099 (0.25)
0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.0098 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
0.130 (3.30) MIN SEATING PLANE
0.015 (0.381) 0.008 (0.204)
0.100 (2.54) BSC
0.070 (1.77) 0.045 (1.15)
-8-
REV. A
PRINTED IN U.S.A.
0.280 (7.11) 0.240 (6.10)
C1942-18-94
2.498

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